1. Field of the Disclosure
The present disclosure relates generally to electronic devices, and more particularly, to electronic devices having a voltage-controlled oscillator.
2. Description of the Related Art
Electronic devices can include oscillators to provide clock signals or other reference signals needed by the electronic device to perform its intended function. A crystal oscillator is often used to provide a signal at a fixed frequency. A phase-locked loop (PLL) can be utilized to provide a signal at an adjustable frequency. A PLL generally includes a voltage-controlled oscillator (VCO) that is calibrated by placing the PLL in an open-loop mode. The frequency of a signal provided by the PLL is adjusted by configuring a divisor implemented by the digital divider accordingly. The open-loop calibration process is repeated when the selected divisor requires a coarse change in the variable capacitance of a variable capacitor of the VCO.
The operating capabilities of a PLL are characterized using specifications including calibration time, lock time, lock range, tuning sensitivity (Kv), noise level, and other attributes. For example, the lock range and the calibration time of a PLL device indicate how quickly the PLL device can respond to a request to alter the frequency of a signal that is provided by the PLL. In particular, if the change in operating frequency exceeds the lock range, a calibration procedure may need to be performed. The correct operation of an electronic device may preclude excessive delays necessary to execute a calibration procedure. Unfortunately, attempts to increase the lock range of the PLL device by increasing its tuning sensitivity can be accompanied by a compromised noise level and greater manufacturing cost.